Publications and presentations

This page summarises peer reviewed articles, presentations at conferences and workshops produced by the E2SWITCH project.

publitab

Publications

2017

  1. Liu, C., Han, Q., Glass, S., et al. Experimental $I$ – $V(T)$ and $C$ – $V$ Analysis of Si Planar p-TFETs on Ultrathin Body. IEEE Transactions on Electron Devices 63(12), 5036-5040, 2016. DOI: 10.1109/TED.2016.2619740
  2. Visciarelli, M., Gnani, E., Gnudi, A., Reggiani, S., and Baccarani, G. Design guidelines for GaSb/InAs TFET exploiting strain and device size. Solid-State Electronics 129, 157-162, 2017. DOI: 10.1016/j.sse.2016.11.011
  3. D. Cutaia, K. Moselund, H. Schmid, M. Borg and H. Riel Uniting III-V tunnel FETs with silicon. Compound Semiconductor, 22-02-2017.
  4. Memisevic, E., Hellenbrand, M., Lind, E., et al. Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade. Nano Letters 17(7), 4373-4380, 2017. DOI: 10.1021/acs.nanolett.7b01455
  5. Settino, F., Lanuzza, M., Strangio, S., et al. Understanding the Potential and Limitations of Tunnel FETs for Low-Voltage Analog/Mixed-Signal Circuits. IEEE Transactions on Electron Devices 64(6), 2736-2743, 2017. DOI: 10.1109/TED.2017.2689746
  6. Memisevic, E., Svensson, J., Lind, E., and Wernersson, L. InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors. IEEE Transactions on Electron Devices 64(11), 4746-4751, 2017. DOI: 10.1109/TED.2017.2750763
  7. Sant, S., and Schenk, A. Modeling the Effect of Interface Roughness on the Performance of Tunnel FETs. IEEE Electron Device Letters 38(2), 258-261, 2017. DOI: 10.1109/LED.2016.2636658
  8. Visciarelli, M., Gnani, E., Gnudi, A., Reggiani, S., and Baccarani, G. Impact of Traps and Strain on Optimized n- and p-Type TFETs Integrated on the Same InAs/AlGaSb Technology Platform. IEEE Transactions on Electron Devices 64(8), 3108-3113, 2017. DOI: 10.1109/TED.2017.2711779
  9. Liu, C., Glass, S., Luong, G. V., et al. Experimental Investigation of ${C}$ – ${V}$ Characteristics of Si Tunnel FETs. IEEE Electron Device Letters 38(6), 818-821, 2017. DOI: 10.1109/LED.2017.2695193
  10. Esseni, D., Pala, M., Palestri, P., Alper, C., and Rollo, T. A review of selected topics in physics based modeling for tunnel field-effect transistors. Semiconductor Science and Technology 32(8), 083005, 2017. DOI: 10.1088/1361-6641/aa6fca
  11. Hellenbrand, M., Memisevic, E., Berg, M., Kilpi, O., Svensson, J., and Wernersson, L. Low-Frequency Noise in III–V Nanowire TFETs and MOSFETs. IEEE Electron Device Letters 38(11), 1520-1523, 2017. DOI: 10.1109/LED.2017.2757538
  12. Sant, S., and Schenk, A. Trap-Tolerant Device Geometry for InAs/Si pTFETs. IEEE Electron Device Letters 38(10), 1363-1366, 2017. DOI: 10.1109/LED.2017.2740262
  13. Schmid, H., Cutaia, D., Gooth, J., et al. Monolithic integration of multiple III-V semiconductors on Si for MOSFETs and TFETs. 2016 IEEE International Electron Devices Meeting (IEDM) , 2016. DOI: 10.1109/IEDM.2016.7838340

2016

  1. Sant, S., Moselund, K., Cutaia, D., et al. Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 2: Simulation Study of the Impact of Interface Traps. IEEE Transactions on Electron Devices 63(11), 4240-4247, 2016. DOI: 10.1109/TED.2016.2612484
  2. Sant, S., and Schenk, A. Methods to Enhance the Performance of InGaAs/InP Heterojunction Tunnel FETs. IEEE Transactions on Electron Devices 63(5), 2169-2175, 2016. DOI: 10.1109/ted.2015.2489844
  3. Moselund, K. E., Cutaia, D., Schmid, H., et al. Lateral InAs/Si p-Type Tunnel FETs Integrated on Si—Part 1: Experimental Devices. IEEE Transactions on Electron Devices 63(11), 4233-4239, 2016. DOI: 10.1109/TED.2016.2606762
  4. Gnani, E., Baravelli, E., Maiorano, P., Gnudi, A., Reggiani, S., and Baccarani, G. Steep-Slope Devices: Prospects and Challenges. Journal of Nano Research 39, 3-16, 2016. DOI: 10.4028/www.scientific.net/JNanoR.39.3
  5. Baccarani, G., Gnani, E., Gnudi, A., and Reggiani, S. Theoretical analysis and modeling for nanoelectronics. Solid-State Electronics 125, 2-13, 2016. DOI: 10.1016/j.sse.2016.07.020
  6. Alper, C., Palestri, P., Padilla, J. L., and Ionescu, A. M. The Electron-Hole Bilayer TFET: Dimensionality Effects and Optimization. IEEE Transactions on Electron Devices 63(6), 2603-2609, 2016. DOI: 10.1109/TED.2016.2557282
  7. Alper, C., Palestri, P., Padilla, J. L., and Ionescu, A. M. Underlap counterdoping as an efficient means to suppress lateral leakage in the electron–hole bilayer tunnel FET. Semiconductor Science and Technology 31(4), 045001, 2016. DOI: 10.1088/0268-1242/31/4/045001
  8. Strangio, S., Palestri, P., Lanuzza, M., Esseni, D., Crupi, F., and Selmi, L. Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits. Solid-State Electronics , 2016. DOI: 10.1016/j.sse.2016.10.022
  9. Luong, G. V., Narimani, K., Tiedemann, A. T., et al. Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity. IEEE Electron Device Letters 37(8), 950-953, 2016. DOI: 10.1109/LED.2016.2582041
  10. Ilatikhameneh, H., Klimeck, G., and Rahman, R. Can Homojunction Tunnel FETs Scale Below 10 nm?. IEEE Electron Device Letters 37(1), 115-118, 2016. DOI: 10.1109/LED.2015.2501820
  11. Schulte-Braucks, C., von den Driesch, N., Glass, S., et al. Low Temperature Deposition of High-k/Metal Gate Stacks on High-Sn Content (Si)GeSn-Alloys. ACS Applied Materials & Interfaces 8(20), 13133-13139, 2016. DOI: 10.1021/acsami.6b02425
  12. Luong, G., Strangio, S., Tiedemannn, A., et al. Experimental demonstration of strained Si nanowire GAA n-TFETs and inverter operation with complementary TFET logic at low supply voltages. Solid-State Electronics 115, 152-159, 2016. DOI: 10.1016/j.sse.2015.08.020
  13. Narimani, K., Luong, G. V., Schulte-Braucks, C., et al. Current mirrors with strained Si single nanowire gate all around Schottky barrier MOSFETs. 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) , 2016. DOI: 10.1109/ULIS.2016.7440082
  14. Cutaia, D., Schmid, H., Borg, M., et al. Investigation of doping in InAs/GaSb hetero-junctions for tunnel-FETs. 2016 IEEE Silicon Nanoelectronics Workshop (SNW) , 2016. DOI: 10.1109/SNW.2016.7578028
  15. Visciarelli, M., Gnani, E., Gnudi, A., Reggiani, S., and Baccarani, G. Impact of Strain on Tunneling Current and Threshold Voltage in III–V Nanowire TFETs. IEEE Electron Device Letters 37(5), 560-563, 2016. DOI: 10.1109/LED.2016.2539389
  16. Visciarelli, M., Gnani, E., Gnudi, A., Reggiani, S., and Baccarani, G. Optimization of GaSb/InAs TFET exploiting different strain configurations. 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) , 2016. DOI: 10.1109/ULIS.2016.7440041
  17. Strangio, S., Palestri, P., Lanuzza, M., Crupi, F., Esseni, D., and Selmi, L. Assessment of InAs/AlGaSb Tunnel-FET Virtual Technology Platform for Low-Power Digital Circuits. IEEE Transactions on Electron Devices 63(7), 2749-2756, 2016. DOI: 10.1109/TED.2016.2566614
  18. Memisevic, E., Svensson, J., Lind, E., and Wernersson, L. InAs/GaSb vertical nanowire TFETs on Si for digital and analogue applications. 2016 IEEE Silicon Nanoelectronics Workshop (SNW) , 2016. DOI: 10.1109/SNW.2016.7578029
  19. Cutaia, D., Schmid, H., Borg, M., et al. Investigation of doping in InAs/GaSb hetero-junctions for tunnel-FETs. 2016 IEEE Silicon Nanoelectronics Workshop (SNW) , 2016. DOI: 10.1109/SNW.2016.7578028

2015

  1. Memisevic, E., Svensson, J., Hellenbrand, M., Lind, E., and Wernersson, L. Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si. IEEE Electron Device Letters 37(5), 549-552, 2016. DOI: 10.1109/LED.2016.2545861
  2. Villani, F., Gnani, E., Gnudi, A., Reggiani, S., and Baccarani, G. A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs. Solid-State Electronics 113, 86-91, 2015. DOI: 10.1016/j.sse.2015.05.018
  3. Caruso, E., Lizzit, D., Osgnach, P., Esseni, D., Palestri, P., and Selmi, L. Simulation analysis of III–V n-MOSFETs: Channel materials, Fermi level pinning and biaxial strain. 2014 IEEE International Electron Devices Meeting , 2014. DOI: 10.1109/IEDM.2014.7047006
  4. Alper, C., Palestri, P., Lattanzio, L., Padilla, J. L., and Ionescu, A. M. Two dimensional quantum mechanical simulation of low dimensional tunneling devices. 2014 44th European Solid State Device Research Conference (ESSDERC) , 2014. DOI: 10.1109/ESSDERC.2014.6948791
  5. Cutaia, D., Moselund, K. E., Borg, M., et al. Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates. IEEE Journal of the Electron Devices Society 3(3), 176-183, 2015. DOI: 10.1109/JEDS.2015.2388793
  6. M. Lanuzza, S. Strangio, F. Crupi, P. Palestri, D. Esseni. Mixed Tunnel-FET/MOSFET Level Shifters: a new proposal to extend the Tunnel-FET application domain. IEEE Transactions on Electron Devices. Vol.62, no.12, pp.3973-3979, 2015. DOI: 10.1109/TED.2015.2494845
  7. Esseni, D. ; Pala, M.G. ; Rollo, T. Essential Physics of the OFF-State Current in Nanoscale MOSFETs and Tunnel FETs. IEEE Transactions on Electron Devices. Vol. 62, n. 9, pages 3084-91, 2015. DOI: 10.1109/TED.2015.2458171
  8. C. Alper, P. Palestri, L. Lattanzio, J.L. Padilla, A.M. Ionescu. Two dimensional quantum mechanical simulation of lowdimensional tunneling devices. Solid-State Electronics, Vol 113, 167-172, 2015, DOI: 10.1016/j.sse.2015.05.030
  9. Cem Alper , Michele Visciarelli, Pierpaolo Palestri, Jose L. Padilla , Antonio Gnudi, Elena Gnani, Adrian M. Ionescu. Modeling the Imaginary Branch in III-V Tunneling Devices: Effective Mass vs k · p. SISPAD 2015, Washington D.C.. 273-276, 2015, DOI: 10.1109/SISPAD.2015.7292312
  10. C. Schulte-Braucks, et al., Negative differential resistance in direct bandgap GeSn p-i-n structures. Journal of Applied Physics. 117, 2015. DOI: 10.1063/1.4927622
  11. Hamilton Carrillo-Nunez, Anne Ziegler, Mathieu Luisier, Andreas Schenk. Modeling direct band-to-band tunneling: from bulk to quantum-confined semiconductor devices. Journal of Applied Physics. 117, 234501_1-10, 2015. DOI: 10.1063/1.4922427
  12. Lind, E.; Memisevic, E.; Dey, A.W.; Wernersson, L.-E. III-V Heterostructure Nanowire Tunnel FETs. Electron Devices Society, IEEE Journal of the vol.3, no.3, pp.96-102, May 2015. DOI: 10.1109/JEDS.2015.2388811
  13. Sant, S.; Schenk, A. Band-Offset Engineering for GeSn-SiGeSn Hetero Tunnel FETs and the Role of Strain. Electron Devices Society, IEEE Journal of the vol.3, no.3, pp.164-175, May 2015. DOI: 10.1109/JEDS.2015.2390971
  14. S. Richter, S. Trellenkamp, A. Schäfer, J. M. Hartmann, K. K. Bourdelle, Q. T. Zhao, S. Mantl. Improved Tunnel-FET Inverter Performance with SiGe/Si Heterostructure Nanowire TFETs by Reduction of Ambipolarity. Solid-State Electronics Volume 108, , Pages 97–103, June 2015 DOI: 10.1016/j.sse.2015.02.018
  15. M. Borg, H. Schmid, K.E. Moselund, D. Cutaia, H. Riel. Mechanisms of Template-Assisted Selective Epitaxy of InAs nanowires on Si. J. Appl. Phys. 117, 144303 (2015) DOI: 10.1063/1.4916984
  16. Villani, F.; Gnani, E.; Gnudi, A.; Reggiani, S.; Baccarani, G. A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs. Solid State Device Research Conference (ESSDERC), 2014 44th European pp.262-265, 22-26 Sept. 2014 DOI: 10.1109/ESSDERC.2014.6948810
  17. P. Palestri, E. Caruso, F. Driussi, D. Esseni, D. Lizzit, P. Osgnach, S. Venica, L. Selmi. State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors. Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2015 38th International Convention on pp.1-8, 25-29 May 2015 DOI: 10.1109/MIPRO.2015.7160227
  18. S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi. Mixed device-circuit simulations of 6T/8T SRAM cells employing tunnel-FETs. Gruppo Italiano di Elettronica 47th Annual Meeting, Proceedings of the; GE 2015 pp. 81-82
  19. P. Palestri, E. Caruso, F. Driussi, D. Esseni, D. Lizzit, P. Osgnach, S. Venica, L. Selmi. State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors. Information and Communication Technology, Electronics and Microelectronics (MIPRO), 2015 38th International Convention on pp.1-8, 25-29 May 2015 DOI: 10.1109/MIPRO.2015.7160227
  20. Schmid, H.; Borg, M.; Moselund, K.; Gignac, L.; Breslin, C.; Bruley, J.; Cutaia, D.; Riel, H. III–V device integration on Si using template-assisted selective epitaxy. Device Research Conference (DRC), 2015 73rd Annual vol., no., pp.255-256, 21-24 June 2015 DOI: 10.1109/DRC.2015.7175666
  21. M. Borg, H. Schmid, K.E. Moselund, D. Cutaia, H. Riel. Mechanisms of Template-Assisted Selective Epitaxy of InAs nanowires on Si. J. Appl. Phys. 117, 144303 (2015) DOI: 10.1063/1.4916984
  22. Baravelli E., Gnani E. , Gnudi A., Reggiani S., Baccarani, G. Capacitance estimation for InAs Tunnel FETs by means of full-quantum k·p simulation. Solid-State Electronics. ULIS Conference Paper. Vol 108, 104-109, 2015. DOI: 10.1016/j.sse.2014.12.005
  23. Sebastiano Strangio, Pierpaolo Palestri, David Esseni, Luca Selmi, Felice Crupi, Simon Richter, Qing-Tai Zhao, Siegfried Mantl Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells. Journal of the Electron Devices Society. Vol 3 Issue 3, 223-232, 2015. DOI: 10.1109/JEDS.2015.2392793
  24. D.Cutaia, K.E.Moselund, M.Borg, H.Schmid, L.Gignac, C.M.Breslin, S.Karg, E.Uccelli, H.Riel. Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates. Journal of Electron Device Society (J-EDS). Vol. 3, Issue 3, 176 - 183, 2015. DOI: 10.1109/JEDS.2015.2388793
  25. S. Wirths et al., Ternary and quaternary Ni(Si)Ge(Sn) contact formation for highly strained Ge p- and n- MOSFETs. Semiconductor Science and technology, Vol 30, Issue 5, 2015
  26. Cem Alper, Pierpaolo Palestri, Jose L Padilla, Antonio Gnudi, Roberto Grassi, Elena Gnani, Mathieu Luisier, Adrian M Ionescu, Efficient quantum mechanical simulation of band-to-band tunneling. EUROSOI-ULIS 2015. 141-144, 2015. DOI: 10.1109/ULIS.2015.7063793
  27. G.V.Luobg, S. Trellenkamp, K.K. Bourdelle, Q. T. Zhao, S. Mantl Strained Si nanowire GAA n-TFETs for low supply voltages. EUROSOI-ULIS. 2015, 65-68, 2015. DOI: 10.1109/ULIS.2015.7063774
  28. S. Blaeser, S.Richter, S. Wirths, S. Trellenkamp, D. Buca, Q. T. Zhao, S. Experimental demonstration of planar SiGe on Si TFETs with counter doped pocket. EUROSOI-ULIS 2015. 297-300, 2015. DOI: 10.1109/ULIS.2015.7063832
  29. S. Wirths, R. Geiger, N. von den Driesch, G. Mussler, T. Stoica, S. Mantl, Z. Ikonic, M. Luysberg, S. Chiussi, J.M. Hartmann, H. Sigg, J.Faist, D. Buca and D. Grützmacher. Lasing in direct bandgap GeSn alloy grown on Si. Nature Photonics 9, 88 - 92, 2015. DOI: 10.1038/NPHOTON.2014.321
  30. S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi, S. Richter, Q. T. Zhao and S. Mantl. Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells. Journal of Electron Device Society (J-EDS). Vol. 3, Issue 3, 223-232, 2015. DOI: 10.1109/JEDS.2015.2392793
  31. Cutaia, D.; Moselund, K.E.; Borg, M.; Schmid, H.; Gignac, L.; Breslin, C.M.; Karg, S.; Uccelli, E.; Nirmalraj, P.; Riel, H. Fabrication and analysis of vertical p-type InAs-Si nanowire Tunnel FETs. in Ultimate Integration on Silicon (EUROSOI-ULIS), 2015 Joint International EUROSOI Workshop and International Conference on , vol., no., pp.61-64, 26-28 Jan. 2015 DOI: 10.1109/ULIS.2015.7063773
  32. Lars-Erik Wernersson. Narrow Gap Semiconductors: From Nanotechnology to RF-Circuits on Si. J. Appl. Phys. 117, 112810 2015. DOI: 10.1063/1.4913836

2014

  1. S. Wirths et al., High k Gate Stacks on Low Bandgap Tensile Strained Ge and GeSn Alloys for Field-Effect Transistors .Applied Materials & Interfaces. Vol 7 Issue 1, 62-67, 2014, DOI: 10.1021/am5075248
  2. Johannes Svensson, Anil Dey, Daniel Jacobson, Lars-Erik Wernersson III-V Nanowire CMOS Monolithically Integrated on Si. Nano research. Vol 7 Issue 12, 1769-1776, 2014. DOI: 10.1007/s12274-014-0536-6
  3. D. Esseni, M.G. Pala, A. Revelant, P. Palestri, L. Selmi, M.(Oscar) Li, G. Snider, D. Jena, H.G. Xing. Challenges and opportunities in the design of Tunnel FETs: materials, device architectures, and defects. ECS Transactions 64 (6), 581-595, 2014. DOI: 10.1149/06406.0581ecst
  4. Hamilton Carrillo-Nunez, Mathieu Luisier, Andreas Schenk. Analysis of InAs-Si Heterojunction Nanowire Tunnel FETs: Extreme Confinement vs. Bulk. Solid State Device Research Conference (ESSDERC), European 44, 118-119, 2014. DOI: 10.1109/ESSDERC.2014.6948772
  5. A. Revelant, A. Villalon, Y. Wu, A. Zaslavsky, C. Le Royer, H. Iwai, S. Cristoloveanu. Electron-Hole Bilayer TFET: Experiments and Comments. IEEE Transactions on Electron Devices 61(8), 2674-2681, 2014. DOI: 10.1109/TED.2014.2329551
  6. Q. T. Zhao, S. Richter, C. Schulte-Braucks, L. Knoll, S. Blaeser, G.V. Luong, S. Trellenkamp, A. Schäfer, A. Tiedemann, K. K. Bourdelle, S. Mantl. Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications. J. Electronic Devices Society. Vol. 3, Issue 3. 103-114, 2014. DOI: 10.1109/JEDS.2015.2400371
  7. B. Mattias Borg, Heinz Schmid, Kirsten E. Moselund, Giorgio Signorello, Lynne Gignac, John Bruley, Chris Breslin, Pratyush das Kanungo, Peter Werner, Heike Riel. Vertical III-V Nanowire Device Integration on Si(100). Nano Letters 14(4), 1914, 2014. DOI: 10.1021/nl404743j
  8. Saurabh Sant and Andreas Schenk. Pseudopotential calculations of strained-GeSn/SiGeSn hetero-structures. Appl. Phys. Lett. 105 (16), 162101, 2014. DOI: 10.1063/1.4898676
  9. H. Riel, L.-E. Wernersson, M. Hong. J. del Alamo. III-V compound semiconductor transistors – from planar to nanowire structures. MRS Bulletin Vol. 39, Iss. 08, pp 668- 677, 2014. DOI: 10.1557/mrs.2014.137
  10. E. Memisevic, É. Lind, L.-E. Wernersson. Thin electron beam defined hydrogen silsesquioxane spacers for vertical nanowire transistors. J. Vac. Sci. Technol. B 32, 051211, 2014; DOI: 10.1116/1.4895112

prestab

Presentations

2017

  1. A. Schenk, S. Sant, K. Moselund, and H. Riel, How Non-ideality. Effects Deteriorate the Performance of Tunnel FETs, EDTM 2017, Toyama, Japan, 01-03-2017
  2. Lars-Erik Wernersson, Invited talk (no title) EuroSOI/ULILS, 04-04-2017
  3. K. Narimani, S. Glass, T. Rieger, P. Bernardy,N. von den Driesch, S. Mantl, Q.T.Zhao, Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents, EUROSOI/ULIS 2017, 04-04-2017
  4. Lars-Erik Wernersson, Invited talk (no title) VLLSI-TSA, Hsinchu, Taiwan, 26-04-2017
  5. E. Memisevic*, J. Svensson, E. Lind, and L.-E. Wernersson, Statistics of InAs/InGaAsSb/GaSb TFETs with sub-50mV/decade operation at VDS of 0.3V, CSW 2017, Berlin, 18-05-2017
  6. A. Schenk, S. Sant, K. Moselund, and H. Riel, The Impact of Hetero-junction and Oxide-interface Traps on the Performance of InAs/Si Tunnel FETs, IWJT 2017, Kyoto, Japan, 01-06-2017
  7. F. Settino, M. Lanuzza, S. Strangio, F. Crupi, P. Palestri, D. Esseni, A virtual III-V Tunnel FET technology platform for ultra-low voltage comparators and level shifters, PRIME 2017, Giardini Naxos - Taormina, Italy, 12-06-2017
  8. S. Sant, M. Luisier, and A. Schenk, DFT-based Analysis of the Origin of Traps at the InAs/Si (111) Interface, SISPAD Kamakura, Japan, 08-09-2017
  9. A. Schenk, S. Sant, E. Memisevic, K. Moselund, H. Riel, and L.-E. Wernersson, The Impact of Hetero-junction and Oxide-interface Traps on the Performance of InAs/Si and InAs/GaAsSb Nanowire Tunnel FETs, SISPAD Kamakura, Japan, 08-09-2017
  10. S Sant, A Schenk, Modeling the Effect of Surface Roughness on the Performance of Line Tunnel FETs, ESSDERC 2017, Leuven, 11-09-2017
  11. G.V. Luong, S. Strangio, A.T. Tiedemann, P. Bernardy, S. Trellenkamp, P. Palestri, S. Mantl and Q.T. Zhao, Experimental characterization of the Static Noise Margins of strained Silicon complementary Tunnel-FET SRAM, ESSDERC 2017, Leuven, 11-09-2017
  12. Markus Hellenbrand, Elvedin Memišević, Johannes Svensson, Erik Lind, and Lars-Erik Wernersson, Random Telegraph Signal Noise in Tunneling FieldEffect Transistors with S below 60 mV/decade, ESSDERC 2017, Leuven, 11-09-2017

2016

  1. A. Schenk, S. Sant, K. Moselund, and H. Riel III-V-based Hetero Tunnel FETs: A Simulation Study with Focus on Non-ideality Effects 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Wien, Austria. 25-01-2016
  2. S. Strangio P. Palestri ; M. Lanuzza ; D. Esseni ; F. Crupi ; L. Selmi Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Wien, Austria. 27-01-2016
  3. K. Moselund, D. Cutaia. M. Borg, H. Schmid, S. Sant, A. Schenk and H. Riel InAs/Si heterojunction nanowire tunnel FETs monolithically integrated on silicon ICONN, Canberra, Australia. 09-02-2016
  4. Qing-Tai Zhao, Gia Vinh Luong, Sebastian Blaeser, Keyvan Narimani, Stefan Trellenkamp, D. Buca, Siegfried Mantl SiGe/Si Tunnel FETs China Semiconductor Technology International Conference 2016, Shanghai. 13-03-2016
  5. David Esseni Fundamentals, modeling and design of small slope, beyond CMOS transistors for energy efficient integrated circuits Kun Huang Forum on Semic. Science and Technology, Beijing, China. 06-06-2016
  6. Qing-Tai Zhao, Gia Vinh Luong, Keyvan Narimani, Stefan Glass, Chang Liu, Sebastian Blaeser, Christian Schulte-Braucks, Nils von den Driesch, Dan Buca, Siegfried Mantl Si and SiGe Tunnel FETs International SiGe Technology and Device Meeting (ISTDM) 2016, Nagoya, Japan. 10-06-2016
  7. S. Sant, A. Schenk, K. Moselund, and H. Riel Impact of Trap-assisted Tunneling and Channel Quantization on InAs/Si Hetero Tunnel FETs DRC, Delaware, USA. 15-06-2016
  8. S. Sant, H. Carrillo-Nuñez, M. Luisier, and A. Schenk Transfer Matrix Based Semiclassical Model for Fieldinduced and Geometrical Quantum Confinement in Tunnel FETs SISPAD, Nuremberg, Germany. 06-09-2016
  9. Elena Gnani Can strain recover the current degradation induced by traps? Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 11-09-2016
  10. A. Schenk, S. Sant, K. Moselund, and H. Riel Trap-assisted Tunneling - Main Non-ideality Effect in Hetero TFETs Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 11-09-2016
  11. Mathieu Luisier, Cedric Klinkert, and Aron Szabo 2016 STEEP Transistors Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 11-09-2016
  12. Qing Tai Zhao, Gia Vinh Luong, Keyvan Narimani, Stefan Glass, Chang Liu, Siegfried Mantl Si (Ge) based Tunnel FETs Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 11-09-2016
  13. Vinh Luong, Christian Schulte-Braucks, Keyvan Narimani, Chang Liu, Qinghua Han, Thomas Tromm, Dan Buca, Qing-Tai Zhao and Siegfried Mantl Si, Ge-Sn and doped HfOx for steep slope devices Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 11-09-2016
  14. K. Moselund, D. Cutaia, H. Schmid, and H. Riel Complementary III-V heterostructure Tunnel FETs Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 12-09-2016
  15. H. Carrillo-Nuñez, R. Rhyner, M. Luisier, and A. Schenk Effect of Surface Roughness and Phonon Scattering on Extremely Narrow InAs-Si Nanowire TFETs Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 13-09-2016
  16. Tommaso Rollo, David Esseni A few design options for capacitance matching in NC-FETs based on ferroelectric insulators Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 14-09-2016
  17. Chang Liu, Qinghua Han, Gia Vinh Luong, Keyvan Narimani, Stefan Glass, Andreas T. Tiedemann, Stefan Trellenkamp, Wenjie Yu, Xi Wang, Siegfried Mantl and Qing-Tai Zhao Si n-TFETs on ultra thin body with suppressed ambipolarity Steep Transistor Workshop, ESSDERC, Lausanne, Switzerland. 14-09-2016
  18. K. moselund, D. Cutaia, H. Schmid, S. Sant, A. Schenk and H. riel III-V heterojunction nanowire tunnel FETs monolitically integrated on silicon Nano Materials and Devices Conference, Toulouse, France. 10-10-2016
  19. E. Gnani, M. Visciarelli, A. Gnudi, S. Reggiani, G. Baccarani Impact of strain and interface traps on the performance of III-V nanowire TFETs ICSICT 2016, Hangzhou, China. 26-10-2016
  20. Lars-Erick Wemersson IEEE Semiconductor Interface Specialists Conference. 08-12-2016

2015

  1. S. Sant and A. Schenk Semi-classical modeling of the effect of channel quantization and other non-idealities on the performance of Tunnel Field Effect Transistors (invited) IWPSD, Bangalore, India. 09-12-2015
  2. Memisevic, Svensson, Lind, Wernersson InAs-GaSb/Si Energy-Efficient Switches? IEDM Washington, USA. 08-12-2015
  3. J. Cao, D. Logoteta, S. Ozkaya, B. Biel, A. Cresti, M.G. Pala, and D. Esseni International Electron Devices Meeting (IEDM) IEDM Washington, USA. 07-12-2015
  4. S. Blaeser, S. Glass, C. Schulte-Braucks, K. Narimani, N. v. d. Driesch, S. Wirths, A. T. Tiedemann, S. Trellenkamp, D. Buca, Q. T. Zhao, S. Mantl Novel SiGe/Si line tunneling TFET with high Ion at low VDD and constant SS IEDM Washington, USA. 07-12-2015
  5. K. Moselund, D. Cutaia, M. Borg, H. Schmid and H. Riel III-V tunnel FETs integrated on silicon QCom Workshop. 31-11-2015
  6. M. Borg, H. Schmid, K.E. Moselund, D. Cutaia, H. Riel Template-Assisted Selective Epitaxy: Highly controlled III-V nanowire integration on Si Nanowires 2015, Barcelona. 26-10-2015
  7. K. Moselund, D. Cutaia, M. Borg, H. Schmid and H. Riel Beyond CMOS Workshop IMEC, Leuven, Belgium. 16-10-2015
  8. Arnab Biswas, Luca De Michielis, Antonios Bazigos and Adrian Mihai Ionescu Compact modeling of DG-Tunnel FET for Verilog-A Implementation ESSDERC 2015, Graz, Austria. 16-09-2015
  9. K. moselund, D. Cutaia, H. Schmid, M. Borg, S. Sant, A. Schenk and H. Riel Integration of III-V heterostructure tunnel FETs on Si using template assisted selective epitaxy (TASE) Compound Semiconductor Week, Toyama, Japan. 26-06-2015
  10. K. Moselund, D. Cutaia, M. Borg, H. Schmid and H. Riel. Beyond CMOS Workshop, IMEC, Leuven, Belgium. 16-10-2015
  11. Dr. M Foysol Chowdhury, Florin Udrea, A Ionescu, A Biswas. Benchmarking of TFET Analogue Circuits: Sensors applications perspective. Steep Transistors Workshop, Notre-Dame, USA. 05-10-2015
  12. David Esseni. Experimentally reported sub-60mV/dec swing in Tunnel FETs. Notre-Dame, USA. 05-10-2015
  13. Adrian Ionescu. E2SWITCH Project Functional diversification with Tunnel FETs. Notre-Dame, USA. 05-10-2015
  14. Vinh Luong, K. Narimani, Christian Schulte-Braukcs, Stefan Wirths, Dan Buca, Qing Tai Zhao and Siegfried Mantl. Unsere Ziele Das Forschungszentrum Jülich im Fokus Mitglied der Helmholtz-Gemeinschaft TFETs for ultra low power.Notre-Dame, USA. 05-10-2015
  15. Lars-Erick Wemersson. Nanowire Tunnel FETs: Axial or Radial TFETs?. Notre-Dame, USA. 05-10-2015
  16. Kirsten Moselund, Davide Cutaia, Heinz Schmid, Mattias Borg, Heike Riel. Where are we with TFETs?.Notre-Dame, USA. 05-10-2015
  17. D. Esseni, M.Pala, E.Gnani, E.Sangiorgi. 4th Berkeley Symposium on Energy Efficient Electronic Systems. Berkeley University, USA. 01-10-2015
  18. Hamilton Carrillo-Nunez, Mathieu Luisier, Andreas Schenk. Analysis of InAs-Si Heterojunction Double-Gate Tunnel FETs with Vertical Tunneling Paths. ESSDERC 2015, Graz. 16-09-2015
  19. G. Baccarani, E. Baravelli, E. Gnani, A. Gnudi, S. Reggiani. ESSDERC 2015. ESSDERC 2015, Graz. 16-09-2015
  20. David Esseni. Modeling and simulations for the design of nanoscale transistors. Tutorial of the INFOS Conference. 29-06-2015
  21. A. Schenk, S. Sant, K. Moselund, and H. Riel. Comparative Simulation Study of InAs/Si and All-III-V Hetero Tunnel FETs (Invited). ECS, Symposium Device Physics, Chicago. 27-05-2015
  22. Qing-Tai Zhao, Simon Richter, Lars Knoll, Gia Vinh Luong, Sebastian Blaeser, Christian Schulte-Braucks, Anna Schäfer, Stefan Trellenkamp, Dan Buca, Siegfried Mantl. Si Nanowire Tunnel FETs for energy efficient nanoelectronics (invited). ECS Symposium. 25-05-2015
  23. David Esseni. Challenges and opportunities related to innovative material systems in CMOS transistors and Tunnel FETs.European Materials Research Society Spring Meeting 2015; Symposium Z: Nanomaterials and processes for advanced semiconductor CMOS devices. 11-05-2015
  24. D. Cutaia, K. E. Moselund, M. Borg, H. Schmid, L. Gignac, C.M. Breslin, S. Karg, E. Uccelli, P. Nirmalraj, H. Riel. EuroSOI-Ulis 2015. EuroSOI-Ulis, Bologna, Italy. 26-01-2015
  25. Cem Alper , Michele Visciarelli, Pierpaolo Palestri, Jose L. Padilla , Antonio Gnudi, Elena Gnani, Adrian M. Ionescu. Modeling the Imaginary Branch in III-V Tunneling Devices: Effective Mass vs k · p. SISPAD 2015, Washington D.C., 273-276. 2015

2014

  1. Siegfried F. Karg, Philipp Mensch, Bernd Gotsmann, Heinz Schmid, Volker Schmidt, Mattias Borg, Heike E. Riel. Enhancement of Seebeck Coefficient and Thermoelectric Power Factor in One-Dimensional InAs Nanowires. MRS Fall Meeting, Boston, MA, USA, 30-11-2014.
  2. Filippo Gander, Lars-Erik Wernersson, Kirsten Leufgen, E2SWITCH movie. 19-11-2014
  3. Qing-Tai Zhao, Lars Knoll, Simon Richter, Christian Schulte-Braucks, Gia Vinh Luong, Sebastian Bläser, Anna Schäfer, Stefan Trellenkamp and Siegfried Mantl. Strained Silicon nanowire Tunnel FETs and NAND logic. Invited paper at ICSICT, Guilin, China. 29-10-2014
  4. Heike E. Riel. Materials and Devices for Next Generation Electronics at IBM Research - Zurich. IBM - Notre Dame Workshop, Notre Dame University, IN, USA, 10-10-2014.
  5. D. Esseni, M.G. Pala, A. Revelant, P. Palestri, L. Selmi, M.(Oscar) Li, G. Snider, D. Jena and H.G. Xing. 2014. Si, SiGe, and Related Compounds: Materials, Processing, and Devices Symposium. Moon Palace Resort, Cancun, Mexico. 08-10-2014
  6. Adrian M. Ionescu. In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits. European Solid-State Device Research Conference (ESSDERC), Venice, Italy. 26-09-2014
  7. K. E. Moselund, M. Borg, H. Schmid, D. Cutaia and H. Riel . III-V heterostructure TFETs integrated on silicon for low-power electronics . Workshop "In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits", ESSDERC, Venice, Italy , 26-09-2014.
  8. P. Palestri and L. Selmi. Simulation of Tunnel FETs for accurate performance prediction at device and circuit level. Workshop "In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits", ESSDERC, Venice, Italy , 26-09-2014.
  9. Qing-Tai Zhao, Siegfried Mantl, Peter Grtinberg. SiGe strained nanowire tunnel FETs: integration and performance. Workshop "In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits", ESSDERC, Venice, Italy , 26-09-2014.
  10. Morin Dehan. Low power Tunnel FET circuits: challenges and opportunities. Workshop "In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits", ESSDERC, Venice, Italy , 26-09-2014.
  11. Lars-Erick Wemersson. Tunnel FETs for digital and analog/RF applications. Workshop "In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits", ESSDERC, Venice, Italy , 26-09-2014.
  12. Adrian M. Ionescu, Nilay Dagtekin, Amab Biswas. Computing and sensing with steep-slope devices. Workshop "In the Quest of Zero Power: Energy Efficient Computing Devices and Circuits", ESSDERC, Venice, Italy , 26-09-2014.
  13. Heike E. Riel. The future of nanoelectronics. Kompetenznetz Funktionelle Nanostrukturen, Bad Herrenalb, Germany, 25-09-2014.
  14. Adrian Ionescu. EPFL Press Release. Lausanne, Switzerland, 25-09-2014
  15. S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi. Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires. European Solid-State Device Research Conference (ESSDERC), Venice, Italy, pp. 282-285, 25-09-2014.
  16. C. Alper, P. Palestri, L. Lattanzio, J. L. Padilla, A. M. Ionescu. Two Dimensional Quantum Mechanical Simulation of Low Dimensional Tunneling Devices. European Solid-State Device Research Conference (ESSDERC), Venice, Italy, 2014, pp. 186-189, 24-09-2014.
  17. Cem Alper, Pierpaolo Palestri, Livio Lattanzio, Adrian M. Ionescu. Two Dimensional Quantum Mechanical Simulation of Low Dimensional Tunneling Devices. 2014 44th European Solid-State Device Conference, 22-09-2014.
  18. Christian Schulte-Braucks, Simon Richter, Lars Knoll,Luca Selmi, Qing-Tai Zhao and Siegfried Mantl. Experimental demonstration of improved analog device performance in GAA-NW-TFETs. 2014 44th European Solid-State Device Conference (ESSDERC), Venice, 22-09-2014.
  19. Hamilton Carrillo-Nunez, Mathieu Luisier, and Andreas Schenk. Analysis of InAs-Si Heterojunction Nanowire Tunnel FETs: Extreme Confinement versus Bulk. 2014 44th European Solid-State Device Conference (ESSDERC), Venice, Italy, 22-09-2014.
  20. F. Villani, E. Gnani, A. Gnudi, S. Reggiani and G. Baccarani. A quasi 2D semianalytical model for the potential profile in hetero and homojunction tunnel FETs. European Solid-State Device Research Conference (ESSDERC), Venice, Italy, 22-09-2014.
  21. G. Baccarani. Advanced Modeling and Simulation Approaches for Nanoscale FETs. "CMOS Technology at the nm Scale Era" tutorial. ESSDERC, Venice, Italy, 22-09-2014.
  22. Dr. M F Chowdhury. TSensors (Trillion Sensors) Summit Munich. TSensors Summit , Munich, Germany, 15th - 17th Sept 2014.
  23. Saurabh Sant, Qing-Tai Zhao, Dan Buca, Siegfried Mantl, and Andreas Schenk. Analysis of GeSn-SiGeSn Hetero-Tunnel FETs. 2014 International Conference on Simulation of Semiconductor Processes and Devices, Yokohama, Japan, 09-09-2014.
  24. Arnab Biswas, Luca De Michielis, Adrian M. Ionescu. A First Order Capacitance-Voltage model for DG-TFET. International Conference on Simulation of Semiconductor Processes and Devices, Yokohama, Japan, 09-09-2014.
  25. Giorgio Signorello, Emanuel Lörtscher, Petr Khomyakov, Siegfried F. Karg, Dasa Lakshmi Narayana Dheeraj, Bernd Gotsmann, Helge Weman, Heike E. Riel. Inducing a Direct-to-Pseudodirect Bandgap Transition in Wurtzite GaAs Nanowires with Uniaxial Stress. Nanowire Conference 2014, Eindhoven, The Netherlands, 29-08-2014.
  26. Lars-Erik Wernersson. Invited talk at ICPS (International Conference of Physics of Semiconductors). ICPS, Austin, USA, 10-08-2014.
  27. Heike E. Riel, Heinz Schmid, Mattias Borg, Kirsten Moselund, Davide Cutaia, Giorgio Signorello, Philipp Mensch, Siegfried F. Karg, Volker Schmidt, Emanuel Lörtscher, Fabian Menges, Bernd Gotsmann. Semiconducting Nanowires – Growth, Characterization & Devices. International Conference on Superlattices, Nanostructures and Nanodevices, Savannah, GA, USA, 07-08-2014.
  28. Heike E. Riel. Semiconducting Nanowires - From Materials to Devices. Gordon Research Conference, Biddeford, ME, USA, 18-07-2014.
  29. Mattias Borg, Heinz Schmid, Kirsten Moselund, Saurabh Sant, Davide Cutaia, Heike E. Riel. Dynamics of III-V MOVPE inside Nanotube Templates on Si. ICMOVPE XVII, Lausanne, Switzerland, 16-07-2014.
  30. M. Borg, H. Schmid, K.E. Moselund, S. Sant, H. Riel. Dynamics of III-V MOVPE inside nanotube templates on Si. ICMOVPE XVII Lausanne, 13-07-2014.
  31. Heike E. Riel. The Future of Nanoelectronics: New Material, Architectures and Mechanisms. ICMOVPE XVII, Lausanne, Switzerland, 13-07-2014.
  32. Heike E. Riel, Heinz Schmid, Mattias Borg, Kirsten Moselund, Davide Cutaia, Philipp Mensch, Siegfried F. Karg, Volker Schmidt, Giorgio Signorello. Semiconducting Nanowires – From Materials to Devices. CMOS Emerging Technologies Research 2014, Grenoble, France, 07-07-2014.
  33. Simon Richter, Christian Schulte-Braucks, Lars Knoll, Gia Vinh Luong, Anna Schäfer, Stefan Trellenkamp, Qing-Tai Zhao and Siegfried Mantl. Experimental Demonstration of Inverter and NAND Operation in p-TFET logic at Ultra-low Supply Voltages down to VDD = 0.15 V. 72nd Device Research Conference (DRC), UC Santa Barbara, USA, 22-06-2014.
  34. Volker Schmidt, Heike E. Riel. In Quest of a New Nanoelectronic Low Power Switch. International Summer School on Physics at Nanoscale, Devet Skal, Czech Republic, 10-06-2014.
  35. Heike E. Riel. Semiconducting Nanowires - From Materials to Devices. Swiss NanoConvention. Windisch, Switzerland, 21-05-2014.
  36. Baravelli E., Gnani E. , Gnudi A., Reggiani S., Baccarani, G.. 15th International Conference on Ultimate Integration on Silicon, ULIS 2014. Stockholm; Sweden, 07-04-2014.
  37. Filippo Gander, SCIPROM team, all. E2SWITCH project flyer. 01-04-2014
  38. Heike E. Riel, Heinz Schmid, Mattias Borg, Kirsten Moselund, Davide Cutaia, Giorgio Signorello, Siegfried F. Karg, Philipp Mensch, Volker Schmidt. III-V Semiconductor Nanowires for Future Devices. Design, Automation and Test in Europe 2014, Dresden, Germany, 27-03-2014.
  39. Kirsten Moselund, Heinz Schmid, Mattias Borg, Cedric Bessire, Pratyush Das Kanungo, Heike E. Riel. The future of nanoelectronics. 5th International Workshop on Advanced Scanning Probe Microscopy Techniques, Karlsruhe, Germany, 24-02-2014.
  40. Filippo Gander, SCIPROM team, all. E2SWITCH project website. 01-01-2014