The E2SWITCH work plan comprises eight work packages, six of which focus on RTD activities and two on Management, Dissemination and Exploitation activities.

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Click on the Workpackages boxes to show their description

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WP1 deals with the fabrication of TFET devices and logic blocks evaluating new architecture concepts and introducing novel materials to meet the device performance requirements. It covers two independent non-planar device technology platforms with unique advantages: SiGe and Ge TFETs, and III-V heterostructure TFETs. The device and circuit characterisation and optimization are performed in cooperation with: WP2 - for device characterisation, WP3 - for device simulations and WP5 - for circuit design and characterisation.

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WP2 will characterise and analyse the tunnelling and TFET devices fabricated in WP1, in order to extract the device and performance parameters relevant to the logic and analog/RF applications.

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WP3 will develop accurate models and optimize the design of n- and p-type TFETs in Si/SiGe and III-V materials. It will also develop a TCAD framework able to accurately investigate the role of dimensionality in a DOS TFET switch.

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WP4 will propose and investigate, by appropriate modelling and experimental validation, the potential of new TFET architectures. The aim is to push the limits of voltage scaling below 0.25V with deep sub-thermal subthreshold swing over 4-5 decade under the constraints of a required performance.

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WP5 will focus on TFET circuits, encompassing both digital and analog/RF design on the technology platforms of the project, and on possible use of TFET devices as candidates for further CMOS scaling.

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WP6 will concentrate on benchmarking, aiming at an objective estimation of the best potential and use of TFET technology compared to CMOS in digital and analog/RF applications.

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Finally, WP7 will enable the dissemination and exploitation of the E2SWITCH findings and WP8 is devised to ensure lean, efficient and effective management of E2SWITCH.